1. Field of the Invention
The present invention relates to a semiconductor memory device having therein a voltage generating circuit for generating an intermediate voltage by switching a power source voltage when a mode is switched.
2. Description of the Background Art
In a semiconductor memory device such as a DRAM (Dynamic Random Access Memory), a plurality of internal source voltages are generated from an external source voltage extVdd supplied from the outside and are used. For example, a voltage Vddp to be supplied to peripheral circuits including a row decoder and a column decoder, an array operation voltage Vdds to be supplied to a memory array including a plurality of memory cells arranged in a matrix, a boosted voltage Vpp to be supplied to a wordline WL, and the like are generated from the external source voltage extVdd.
In a general DRAM, a precharge voltage Vbl for precharging a bit line for reading out data from a memory cell is generated so as to be the half of the array operation voltage Vdds by referring to the array operation voltage Vdds. A cell plate voltage Vcp to be supplied to one of electrodes (cell plate electrode) of a capacitor as a component of a memory cell is also generated by referring to the array operation voltage Vdds so as to be the half of the array operation voltage Vdds.
FIG. 9 shows a conventional typical half Vdds generating circuit. Referring to FIG. 9, a half Vdds generating circuit 40D has a reference voltage generating circuit 42 and a driver circuit 44. The reference voltage generating circuit 42 has resistors 421 and 424, an N-channel MOS transistor 422, and a P-channel MOS transistor 423. The resistor 421 is connected between a power supply node 425 and a node 427. The N-channel MOS transistor 422 and the P-channel MOS transistor 423 are diode-connected in series between the node 427 and a node 428. The drain terminal of the N-channel MOS transistor 422 is connected to the node 427 and the drain terminal of the P-channel MOS transistor 423 is connected to the node 428.
The resistor 424 is connected between the node 428 and a ground node 426. The resistor 421 has a resistance value R1 and a resistor 424 has a resistance value R2.
The driver circuit 44 is constructed by an N-channel MOS transistor 441 and a P-channel MOS transistor 442. The N-channel MOS transistor 441 is connected between a power source node 443 and an output node 445, and the P-channel MOS transistor 442 is connected between the output node 445 and a ground node 444. The N-channel MOS transistor 441 receives a voltage on the node 427 in the reference voltage generating circuit 42 by its gate terminal. The P-channel MOS transistor 442 receives a voltage on the node 428 in the reference voltage generating circuit 42 by its gate terminal.
In the reference voltage generating circuit 42, the array operation voltage Vdds is supplied from the power supply node 425 and is divided to a voltage determined by a resistance value R1 of the resistor 421 and a voltage determined by a resistance value R2 of the resistor 424. The reference voltage generating circuit 42 outputs a voltage Vnd from the node 427, and outputs a voltage Vpd from the node 428. In this case, the voltages Vnd and Vpd are expressed by the following equations.
Vnd=Vn+Vthn1, Vpd=Vnxe2x88x92|Vthp1|xe2x80x83xe2x80x83(1)
where, Vn denotes a voltage on a node 429, Vthn1 denotes a threshold voltage of the N-channel MOS transistor 422, and Vthp1 denotes a threshold voltage of the P-channel MOS transistor 423.
In the reference voltage generating circuit 42, when the size of the N-channel MOS transistor 422 and that of the P-channel MOS transistor 423 are set to be large with respect to a through current from the power supply node 425 to the ground node 426, a voltage Vn is expressed as the following equation.
Vn=|Vthp1|+(Vddsxe2x88x92Vthn1xe2x88x92|Vthp1|)xc3x97R2/(R1+R2)xe2x80x83xe2x80x83(2)
The voltage Vnd on the node 427 and the voltage Vpd on the node 428 are supplied to the gate terminals of the N-channel MOS transistor 441 and the P-channel MOS transistor 442 in the driver circuit 44, respectively. In the case where a threshold voltage of the N-channel MOS transistor 441 and that of the P-channel MOS transistor 442 are set as Vthn2 and Vthp2, respectively, when Vblxe2x88x92Vpd greater than |Vthp2|, the P-channel MOS transistor 442 is turned on, a current flows from the output node 445 to the ground node 444, and the precharge voltage Vbl decreases. When Vndxe2x88x92Vbl greater than Vthn2, the N-channel MOS transistor 441 is turned on, a current flows from the power source node 443 to the output node 445, and the precharge voltage Vbl increases. The voltage level of the precharge voltage Vbl is therefore controlled by the voltages Vnd and Vpd supplied from the reference voltage generating circuit 42.
When Vthn1=Vthn2 and Vthp1=Vthp2 are satisfied, Vbl is equal to Vn from the equations (1) and (2), and the voltage level of the precharge voltage Vbl desired to be generated is determined by the resistance values R1 and R2. Particularly, when R1=R2 and Vthn1=Vthp1 are satisfied at the same time, Vbl=Vdds/2, that is, the precharge voltage Vbl is equal to just the half of the array operation voltage Vdds.
By determining as described above the resistance values R1 and R2 of the resistors 421 and 424 of the reference voltage generating circuit 42, the threshold voltages Vthn1 and Vthp1 of the N-channel MOS transistor 422 and the P-channel MOS transistor 423, and the threshold voltages Vthn2 and Vthp2 of the N-channel MOS transistor 441 and the P-channel MOS transistor 442 of the driver circuit 44, the half Vdds generating circuit 40D generates the precharge voltage Vbl and the cell plate voltage Vcp each of which is the half of the array operation voltage Vdds.
In a normal mode of the DRAM, each of the precharge voltage Vbl and the cell plate voltage Vcp is controlled to be the half of the array operation voltage Vdds. In the case where the array operation voltage fluctuates, the precharge voltage Vbl and the cell plate voltage Vcp accordingly fluctuate so as to follow the fluctuation in the array operation voltage Vdds.
In a test mode, however, when the precharge voltage Vbl and the cell plate voltage Vcp fluctuate with the array operation voltage Vdds, a problem such that an accurate test of a memory cell cannot be conducted occurs.
For example, in some tests, the array operation voltage Vdds is increased only by xcex94Vdds to carry out a margin test of memory cells. Referring to FIG. 10, the array operation voltage Vdds is increased only by xcex94Vdds at time T0 and is reset to a normal value at time T1. If the period from T0 to T1 is sufficiently long, the precharge voltage Vbl increases by xcex94Vdds/2.
Generally, a parasitic capacity of the precharge voltage Vbl is much larger than that of the array operation voltage Vdds. Consequently, even when the array operation voltage Vdds is reset to the normal value by time T2 at which an operation test of a memory cell is to be conducted, the precharge voltage Vbl is not yet reset to the normal value. The voltage of a pair of bit lines BL and /BL of a memory cell from which data is read is therefore higher than the precharge voltage Vbl. This influences a sense operation performed at the time of reading data from the memory cell. When it is assumed that H-level data is read from a memory cell to the bit line BL, a voltage difference between the bit lines, BL and /BL, becomes smaller than that in the normal mode. It makes difficult for a sense amplifier to amplify the voltage difference to the full level, Vdds and ground.
This problem occurs also in the case where the array operation voltage Vdds is made lower than a normal value for a predetermined period and, after that, data of an L (logic low) level is read from a memory cell.
There are also cases that only the precharge voltage Vbl is desired to be changed independently. However, in the conventional half Vdds generating circuit shown in FIG. 9, the precharge voltage Vbl follows the array voltage.
Consequently, in the case of supplying the precharge voltage Vbl of an arbitrary voltage level to a memory cell, a pad is prepared and the precharge voltage Vbl having an arbitrary voltage level is supplied by using a driver such as a tester from the outside.
However, in the case where a pad is disposed in a position quite different from the half Vdds generating circuit, resistance in a Vbl interconnection to the memory cell in the normal mode and that in the test mode are different from each other. When the precharge voltage Vbl is supplied from the pad, a problem such that an operation test of a memory cell adapted to an actual use state cannot be conducted occurs.
It is therefore an object of the invention to provide a semiconductor memory device having therein a voltage generating circuit capable of switching a voltage used as a reference to generate an intermediate voltage between a normal mode and a test mode.
According to the invention, there is provided a semiconductor memory device in which data is inputted/outputted to/from a plurality of memory cells included in a memory array, including: an external source terminal to which an external source voltage is inputted; a first voltage generating circuit for generating an internal source voltage on the basis of the external source voltage; and a second voltage generating circuit for generating an intermediate voltage as a voltage which is between the internal source voltage or reference voltage and a ground voltage and is necessary for inputting/outputting data to/from the plurality of memory cells, wherein the second voltage generating circuit generates the intermediate voltage in response to a voltage level of the internal source voltage in a normal mode, and generates the intermediate voltage in response to a voltage level of the reference voltage in a test mode.
In the semiconductor memory device according to the invention, the second voltage generating circuit generates the intermediate voltage by using a voltage which varies according to the normal mode and the test mode, and data is inputted/outputted to/from the plurality of memory cells. Therefore, according to the invention, the intermediate voltage following the internal source voltage in the normal mode can be controlled independently in the test mode.
Preferably, the second voltage generating circuit in the semiconductor memory device includes: a reference voltage generating circuit for generating a first reference voltage in response to a voltage level of the internal source voltage in the normal mode and generating a second reference voltage in response to a voltage level of the reference voltage in the test mode; and a driver circuit for outputting the intermediate voltage by supplying a current in response to a voltage level of the first or second reference voltage from a power source node.
By supplying a current from the power source node, the voltage level of the intermediate voltage can be held at a predetermined level. The current supplied from the source node is controlled by the first or second reference voltage. Therefore, according to the invention, the current supplied to generate the intermediate voltage can be controlled by the voltage. As a result, by supplying the voltage varying between the normal mode and the test mode to the circuit for generating an intermediate voltage, the intermediate voltage can be controlled independent of the internal source voltage.
Preferably, the semiconductor memory device further includes a control circuit for generating a first logic signal having a first logic level in the normal mode, and generating a second logic signal having a second logic level different from the first logic level in the test mode. The reference voltage generating circuit generates the first reference voltage in accordance with the first logic signal and generating the second reference voltage in accordance with the second logic signal.
In the normal mode, when the logic signal having the first logic level is received, the reference signal generating circuit generates the first reference voltage obtained by using the internal source voltage as a reference. In the test mode, when the logic signal having the second logic level is received, the reference voltage generating circuit generates the intermediate voltage obtained by using the reference voltage as a reference. Thus, according to the invention, the voltage as a reference to generate the intermediate voltage can be switched by the logic signal.
Preferably, the reference voltage generating circuit includes: a first node; a second node; a first voltage dividing circuit for dividing the internal source voltage to generate a first voltage and a second voltage; a second voltage dividing circuit for dividing the reference voltage to generate a third voltage and a fourth voltage; and a selecting circuit for outputting the first and second voltages to the first and second nodes, respectively, in response to the first logic signal and outputting the third and fourth voltages to the first and second nodes, respectively, in response to the second logic signal. The driver circuit includes: an output node; a first current supplying circuit for supplying a current from the power source node to the output node in response to a voltage level on the first node; and a second current supplying circuit for supplying a current from the output node to a ground node in response to a voltage level on the second node.
In the normal mode, the two voltages obtained by dividing the intermediate source voltage are supplied as first reference voltages to the driver circuit, and a current according to the voltage level of the two voltages is supplied from the source node. In the test mode, the two voltages obtained by dividing the reference voltage are supplied as second reference voltages to the driver circuit, and a current according to the voltage level of the two voltages is supplied from the source node. Therefore, according to the invention, a reference voltage can be easily generated.
Preferably, the first voltage dividing circuit includes: a third node corresponding to the first node; a fourth node corresponding to the second node; a first resistor connected between a power source node to which the internal source voltage is supplied and the third node; first and second MOS transistors of different conduction types diode-connected in series between the third and fourth nodes; and a second resistor connected between the fourth node and a ground node. The second voltage dividing circuit has: a fifth node corresponding to the first node; a sixth node corresponding to the second node; a third resistor connected between the power source node to which the internal source voltage is supplied and the fifth node; third and fourth MOS transistors of different conduction types diode-connected in series between the fifth and sixth nodes; and a fourth resistor connected between the sixth node and a ground node. The first current supplying circuit includes a fifth MOS transistor of a first conduction type for receiving a voltage on the first node by a gate terminal, and the second current supplying circuit includes a sixth MOS transistor of a second conduction type for receiving a voltage on the second node by a gate terminal.
Each of the reference voltage generating circuit and the driver circuit is constructed by using a resistor and a MOS transistor. Thus, the voltage generating circuit for generating a voltage which varies between the normal mode and the test mode can be fabricated by using the same devices as those of a memory cell.
Preferably, the semiconductor memory device further includes a control circuit for generating a first logic signal having a first logic level in the normal mode, and generating a second logic signal having a second logic level different from the first logic level in the test mode. The reference voltage generating circuit receives the internal source voltage supplied and generates the first reference voltage in accordance with the first logic signal, and receives the reference voltage supplied and generates the second reference voltage in accordance with the second logic signal.
In the normal mode, the internal source voltage is supplied, and the reference voltage generating circuit generates the first reference voltage on the basis of the supplied internal source voltage. In the test mode, the reference voltage is supplied, and the reference voltage generating circuit generates a second reference voltage on the basis of the reference voltage. The driver circuit outputs the intermediate voltage by supplying the current according to the first or second reference voltage from the source node. That is, the source voltage to be supplied to the reference voltage generating circuit can be switched between the normal mode and the test mode.
Therefore, according to the invention, intermediate voltages can be generated by using different voltages by a single reference voltage generating circuit.
Preferably, the reference voltage generating circuit includes: a voltage supplying circuit for supplying the internal source voltage in response to the first logic signal and supplying the reference voltage in response to the second logic signal; and a voltage dividing circuit for dividing the internal source voltage received from the voltage supplying circuit to generate the first reference voltage and dividing the reference voltage received from the voltage supplying circuit to generate the second reference voltage.
In the normal mode, the internal source voltage is divided to generate the first reference voltage. In the test mode, the reference voltage is divided to generate the second reference voltage. Therefore, according to the invention, by dividing the voltage which varies between the normal mode and the test mode, the intermediate voltages can be generated by using different voltages as a reference.
Preferably, the voltage supplying circuit includes: a first power source node to which the internal source voltage is supplied; a second power source node to which the reference voltage is supplied; a supply node for supplying the internal source voltage or the reference voltage; a first device for receiving the first logic signal and supplying the internal source voltage supplied to the first power source node to the supply node; and a second device for receiving the second logic signal and supplying the reference voltage supplied to the second power source node to the supply node. The voltage dividing circuit has: a first node; a second node; and a voltage dividing device for, when the first logic signal is received, dividing the internal source voltage to generate first and second voltages, and outputting the generated first and second voltages to the first and second nodes, respectively, when the second logic signal is received, dividing the reference voltage to generate third and fourth voltages, and outputting the generated third and fourth voltages to the first and second nodes, respectively. The driver circuit includes: an output node; a first current supplying device for supplying a current from the power source node to the output node in response to a voltage level on the first node; and a second current supplying device for supplying a current from the output node to a ground node in response to a voltage level on the second node.
The voltage which varies between the normal mode and the test mode is divided to generate two voltages, and the generated two voltages are supplied to the driver circuit. In the driver circuit, a current according to the voltage level of one of the supplied two voltages flows from the source node to the output node, and a current according to the voltage level of the other voltage flows from the output node to the ground node. Therefore, according to the invention, the intermediate voltage can be held constant by two voltages.
Preferably, the semiconductor memory device further includes a third voltage generating circuit for generating another internal source voltage on the basis of the external source voltage and supplying the generated another internal source voltage as the reference voltage to the second voltage generating circuit.
In each of the normal mode and the test mode, the intermediate voltage is outputted by using the internal source voltage generated on the inside as a reference. Therefore, according to the invention, the voltage used as a reference to generate the intermediate voltage can be switched on the inside.
Preferably, the second voltage generating circuit supplies the intermediate voltage to one of electrodes of a capacitor included in each of the plurality of memory cells.
The voltage supplied to one of the electrodes of the capacitor for holding information in a memory cell is switched between the normal mode and the test mode. Therefore, according to the invention, even when the voltage as a reference for generating the intermediate voltage fluctuates in the normal mode, the operation test on memory cells can be conducted with accuracy.
Preferably, the second voltage generating circuit supplies the intermediate voltage as a bit line pair precharging voltage for precharging a pair of bit lines provided in correspondence with the plurality of memory cells to the memory array.
The bit line pair precharging voltage for precharging a pair of bit lines is switched between the normal mode and the test mode. Therefore, according to the invention, even when the voltage as a reference to generate an intermediate voltage fluctuates in the normal mode, the operation of sensing data read from a memory cell can be conducted with accuracy.
Preferably, the semiconductor memory device further includes a reference voltage terminal to which the reference voltage is supplied.
In the test mode, the voltage used as a reference to generate an intermediate voltage is supplied from the outside. Therefore, according to the invention, the voltage level of the intermediate voltage to be generated in the test mode can be arbitrarily controlled.
Preferably, the prescribed voltage terminal receives in the normal mode a signal different in purpose from that of a signal received by the presecribed voltage termianl in the test mode.
By using the terminal for receiving a signal in the normal mode, the voltage used as a reference to generate the intermediate voltage is supplied in the test mode. Therefore, the semiconductor memory device capable of switching a voltage as a reference to generate the intermediate voltage can be fabricated without enlarging the chip size.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.